Localized masking for semiconductor structure development

ABSTRACT

Container structures for use in integrated circuits and methods of their manufacture without the use of mechanical planarization such as chemical-mechanical planarization (CMP), thus eliminating CMP-induced defects and variations. The methods utilize localized masking of holes for protection of the inside of the holes during non-mechanical removal of exposed surface layers. The localized masking is accomplished through differential exposure of a resist layer to electromagnetic or thermal energy. The container structures are adapted for use in memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.

[0001] This application is a divisional of U.S. application Ser. No.09/912,151 filed on Jul. 24, 2001 which is a divisional of U.S.application Ser. No. 09/258,471 filed on Feb. 26, 1999 now issued asU.S. Pat. No. 6,358,793 on Mar. 19, 2002. These applications areincorporated herein by reference.

TECHNICAL FIELD

[0002] The present invention relates generally to development ofsemiconductor structures and in particular to development ofsemiconductor container structures using localized masking techniques.

BACKGROUND

[0003] Semiconductors are used extensively in today's electronicdevices. Their miniature size and low power requirements enable highlycomplex circuits to be used in places never before thought possible.This has led to the development of systems with the speed and power tomake our lives easier without encumbering us with bulky boxes andpower-hungry electronics. One of the keys to both light weight andenergy efficiency is the tiny size of the circuitry. With each newgeneration of circuit technology, comes smaller and smaller devicesizes.

[0004] Many electronic systems include a memory device, such as aDynamic Random Access Memory (DRAM), to store data. A typical DRAMincludes an array of memory cells. Each memory cell includes a capacitorthat stores the data in the cell and a transistor that controls accessto the data. The capacitor includes two conductive plates. The top plateof each capacitor is typically shared, or common, with each of the othercapacitors. This plate is referred to as the “top cell plate.” Thecharge stored across the capacitor is representative of a data bit andcan be either a high voltage or a low voltage. Data can be either storedin the memory cells during a write mode, or data may be retrieved fromthe memory cells during a read mode. The data is transmitted on signallines, referred to as digit lines, which are coupled to input/output(I/O) lines through transistors used as switching devices. Typically,for each bit of data stored, its true logic state is available on an I/Oline and its complementary logic state is available on an I/O complementline. Thus, each such memory cell has two digit lines, digit and digitcomplement.

[0005] Typically, the memory cells are arranged in an array and eachcell has an address identifying its location in the array. The arrayincludes a configuration of intersecting conductive lines, and memorycells are associated with the intersections of the lines. In order toread from or write to a cell, the particular cell in question must beselected, or addressed. The address for the selected cell is representedby input signals to a word line decoder and to a digit line decoder. Theword line decoder activates a word line in response to the word lineaddress. The selected word line activates the access transistors foreach of the memory cells in communication with the selected word line.The digit line decoder selects a digit line pair in response to thedigit line address. For a read operation, the selected word lineactivates the access transistors for a given word line address, and datais latched to the digit line pairs.

[0006] Some circuit devices utilize “container” structures, and suchcontainer structures are often utilized as a capacitor for a memory celldue to their efficient use of semiconductor die real estate. Afterformation, these container structures look like tiny holes within thesurrounding material. They will generally have a closed bottom, an opentop and sidewalls extending between the closed bottom and open top.Typically, containers that will be formed into capacitor structures willhave dimensions that are taller than they are wide, often referred to asa “high aspect-ratio.” This high aspect-ratio of container capacitorscan allow the capacitor to store more energy while maintaining the sametwo-dimensional surface area. Conversely, the diameter of the hole canbe reduced with no impact on energy storage to reduce the requiredsurface area for the device. This allows for faster, smaller, and moreenergy-efficient devices to be constructed.

[0007] In order to further increase a container capacitor's ability tostore energy, semiconductor manufacturers have moved towards atechnology using hemispherical grain (HSG) polysilicon. HSG polysiliconprocessing provides a roughened surface, with individual grains ofpolysilicon protruding from the surface of the film inside thecontainer, thereby increasing the effective surface area of thecapacitor formed of the container. The combination of using highaspect-ratio structures and HSG polysilicon has produced semiconductorswith much higher performance characteristics than previous structures,while maintaining the same amount of die real estate.

[0008] HSG polysilicon processing typically involves a blanket formationof HSG polysilicon over the entire surface of the supporting structurein which the containers are formed. Since the surface HSG polysiliconmust be removed to define the individual container capacitors, thisprogression in technology has also introduced new problems to overcome,i.e., removal of unwanted HSG polysilicon while minimizing theintroduction of defects caused by the removal process.

[0009] For example, container capacitors are usually formed in aninsulating material, such as borophosphosilicate glass (BPSG). Next,traditional Low Pressure Chemical Vapor Deposition (LPCVD) processingdeposits an HSG polysilicon layer over the entire support structure,including the inside of the container capacitor hole and as well as theentire surface of the support structure. The processing may also formHSG polysilicon on the backside of the support structure.

[0010] The HSG polysilicon on the surface and/or backside of the supportstructure is undesirable in the creation of container capacitors. Thetraditional method of removing the undesired HSG polysilicon uses aplanarization process such as chemical-mechanical planarization (CMP).However, concern has arisen over the fact that the CMP process itselfmay inherently cause defects such as chatter marks, scratches, residueand CMP-related particle defects that are left as a result of theslurry. These defects may produce performance characteristics making thesemiconductor structures unusable or of questionable quality andreliability.

[0011] Another concern of the CMP process is that grains of an HSGpolysilicon surface are fragile and can become dislodged during themechanical planarization process. A dislodged HSG polysilicon grain thatbridges between two container capacitors may cause a cell-to-cell shortleading to charge leakage and resultant improper performance. To helpprotect against such failures, cell formation processing includes theuse of a fill material to mask and protect the container holes duringCMP removal of surface HSG, as well as during subsequent removal of thesurrounding BPSG. However, such techniques are not entirely effectiveagainst the mechanical strains induced by CMP.

[0012] A method of forming a patterned seed layer in trenches has beenproposed by Schinella et al. in U.S. Pat. No. 5,670,425 issued Sep. 23,1997. Schinella et al. relates to the forming of local areainterconnects in an integrated circuit structure by selective depositionof certain conductive metal compounds over a seed layer previouslyformed in one or more trenches in an insulation layer wherein the one ormore trenches have been previously formed in a pattern conforming to thedesired interconnect configuration, so that the objectionable step ofpatterning a blanket deposited layer of a conductive metal compound canbe eliminated. In accordance with one embodiment of the invention ofSchinella et al., Schinella et al. propose a process in which aphotoresist layer may be formed over an insulation layer and a seedlayer thereon which will flow into coated trenches as well as over theportions of the seed layer deposited over the top surface of theinsulation layer, forming a planar layer of photoresist. Schinella etal. then propose, in one embodiment, that to expose those portions ofthe seed layer not on a trench surface, the photoresist layer could bepartially exposed to light energy (to only expose the top portion of thephotoresist layer), and then conventionally developed to remove suchexposed top portions of the photoresist layer. The seed layer ofSchinella et al. normally may comprise any electrically conductivematerial which is capable of promoting subsequent selective depositionand/or growth of a conductive metal compound thereon which is capable ofsuch selective deposition and/or growth. Although Schinella et al. doesnot address nor suggest the growth of HSG polysilicon on the seed layerof Schinella et al., HSG polysilicon may be formed using an appropriateseed layer. However, use of a seed layer for formation of HSGpolysilicon results in a film that is stoichiometrically and/orphysically different from blanket-deposited HSG polysilicon.

[0013] As noted above, the fragile nature of the HSG polysilicon grainsurface requires special handling to reduce defects. Furthermore, thecurrent preferred industry method of HSG polysilicon removal involvingCMP may inherently introduce defects in the semiconductor structures.CMP may also result in dimensional variations in a cell array, as wellas unwanted cross-wafer variation due to uneven removal rates.Accordingly, what is needed is a process that preserves the HSGpolysilicon within the container capacitor while reducing defects andvariations associated with the elimination of the surface and backsideHSG polysilicon by conventional CMP.

SUMMARY

[0014] The present invention provides methods for developingsemiconductor container capacitors, and apparatus utilizing suchcontainer capacitors. The invention reduces the defects and costnormally incurred with chemical-mechanical planarization (CMP)processing of container capacitors. The embodiments of the inventionutilize localized masking of the container holes by selective exposureof resist. Although the following description is provided with referenceto container capacitors utilizing hemispherical grain (HSG) polysilicon,it will be recognized by those skilled in the art that the methodspresented herein are equally applicable to other semiconductor containerstructures and materials of construction, as well as other structuresmaking use of such localized masking.

[0015] In one embodiment, a resist layer is formed overlying a firstsupport layer and filling a hole in the first support layer. The resistoverlying the surface of the first support layer is selectively removedby a method including exposing the resist layer to a level of energysufficient to fully expose and develop resist above the sidewalls of thehole, while leaving at least a portion of the resist in the holeunderexposed. In one embodiment, the resist layer is exposed to acontrolled dose of energy, wherein at least a portion of the resist inthe hole remains underexposed. In another embodiment, the resist layeris exposed using energy with an angled incident, wherein at least aportion of the resist in the hole remains underexposed. In a furtherembodiment, the resist layer is exposed using wave energy having awavelength generally incapable of penetrating the hole, wherein at leasta portion of the resist in the hole remains underexposed. In a stillfurther embodiment, the resist layer is exposed using energy with anangled incident and having a wavelength generally incapable ofpenetrating the hole, wherein at least a portion of the resist in thecontainer hole remains underexposed. In one embodiment, a second supportlayer is formed interposed between the resist layer and the firstsupport layer.

[0016] In another embodiment, a resist layer is formed overlying aninsulating layer and filling a container hole. The resist overlying thesurface of the insulating layer is selectively removed by a methodincluding exposing the resist layer to a level of energy sufficient tofully expose and develop resist above the sidewalls of the containerhole, while leaving at least a portion of the resist in the containerhole underexposed. In one embodiment, the resist layer is exposed to acontrolled dose of energy, wherein at least a portion of the resist inthe container hole remains underexposed. In another embodiment, theresist layer is exposed using energy with an angled incident, wherein atleast a portion of the resist in the container hole remainsunderexposed. In a further embodiment, the resist layer is exposed usingat least some wave energy having a wavelength generally incapable ofpenetrating the container hole, wherein at least a portion of the resistin the container hole remains underexposed. In a still furtherembodiment, the resist layer is exposed using energy with an angledincident and having a wavelength generally incapable of penetrating thecontainer hole, wherein at least a portion of the resist in thecontainer hole remains underexposed. In one embodiment, a containerlayer is formed interposed between the resist layer and the insulatinglayer.

[0017] In another embodiment, a resist layer is formed overlying a firstsupport layer and filling a hole. The resist overlying the surface ofthe first support layer is selectively removed by a method includingconducting thermal energy to the hole at an effective transfer ratehigher than the effective transfer rate to the resist above the holesuch that the resist in the hole is selectively hardened or bakedrelative to the resist on the surface. In one embodiment, a secondsupport layer is formed interposed between the resist layer and thefirst support layer.

[0018] In yet another embodiment, a resist layer is formed overlying aninsulating layer and filling a container hole. The resist overlying thesurface of the insulating layer is selectively removed by a methodincluding conducting thermal energy to the container hole at aneffective transfer rate higher than the effective transfer rate to theresist above the container hole such that the resist in the containerhole is selectively hardened or baked relative to the resist on thesurface. In one embodiment, a container layer is formed interposedbetween the resist layer and the insulating layer.

[0019] In a further embodiment, a first resist layer is formed overlyinga first support layer. The first resist layer is of a first resist type.A reticle is used to pattern the first resist layer to define a futurehole. Subsequent to formation of the hole and removal of the firstresist layer, a second resist layer is formed overlying the firstsupport layer and filling the hole. The second resist layer is of asecond resist type opposite the first resist type. The reticle isrealigned over the hole and the second resist layer is patterned.Because the second resist type is opposite the first resist type, andthe same reticle is used to pattern the second resist layer, an oppositepattern is produced in the second resist layer, thus forming a resistplug filling the hole and extending above the sidewalls of the hole. Inone embodiment, a second support layer is formed interposed between thesecond resist layer and the first support layer.

[0020] In a still further embodiment, a first resist layer is formedoverlying an insulating layer. The first resist layer is of a firstresist type. A reticle is used to pattern the first resist layer todefine a future container hole. Subsequent to formation of the containerhole and removal of the first resist layer, a second resist layer isformed overlying the insulating layer and filling the container hole.The second resist layer is of a second resist type opposite the firstresist type. The reticle is realigned over the container hole and thesecond resist layer is patterned. Because the second resist type isopposite the first resist type, and the same reticle is used to patternthe second resist layer, an opposite pattern is produced in the secondresist layer, thus forming a resist plug filling the container hole andextending above the sidewalls of the container. In one embodiment, acontainer layer is formed interposed between the second resist layer andthe insulating layer.

[0021] Further embodiments of the invention include semiconductorstructures produced using one or more methods of the invention, as wellas apparatus, devices, modules and systems making use of suchsemiconductor structures. Such structures are devoid of CMP-inducedvariations and defects.

[0022] It will be recognized that the methods of the various embodimentscan be combined in practice, either concurrently or in succession. Forexample, controlled energy dosage may be combined with angled incidentor energy having wavelengths generally incapable of penetrating thehole. Other permutations and combinations will be readily apparent tothose skilled in the art.

BRIEF DESCRIPTION OF THE DRAWINGS

[0023] FIGS. 1-7 are cross-sectional views of a wafer during variousprocessing stages in accordance with one embodiment of the invention.

[0024] FIGS. 8-10 are cross-sectional views of a wafer during variousprocessing stages in accordance with another embodiment of theinvention.

[0025]FIG. 11 is a cross-sectional view of a wafer in accordance withyet another embodiment of the invention.

[0026]FIG. 12 is a cross-sectional view of a wafer in accordance withstill another embodiment of the invention.

[0027] FIGS. 13-19 are cross-sectional views of a wafer during variousprocessing stages in accordance with a further embodiment of theinvention.

[0028]FIG. 20 is a cross-sectional view of a memory cell containercapacitor in accordance with an embodiment of the invention.

[0029]FIG. 21 is a block diagram of an integrated circuit memory devicein accordance with an embodiment of the invention.

[0030]FIG. 22 is an elevation view of a wafer containing semiconductordies in accordance with an embodiment of the invention.

[0031]FIG. 23 is a block diagram of an exemplary circuit module inaccordance with an embodiment of the invention.

[0032]FIG. 24 is a block diagram of an exemplary memory module inaccordance with an embodiment of the invention.

[0033]FIG. 25 is a block diagram of an exemplary electronic system inaccordance with an embodiment of the invention.

[0034]FIG. 26 is a block diagram of an exemplary memory system inaccordance with an embodiment of the invention.

[0035]FIG. 27 is a block diagram of an exemplary computer system inaccordance with an embodiment of the invention.

DESCRIPTION OF THE EMBODIMENTS

[0036] In the following detailed description of the preferredembodiments, reference is made to the accompanying drawings which form apart hereof, and in which is shown by way of illustration specificembodiments in which the inventions may be practiced. These embodimentsare described in sufficient detail to enable those skilled in the art topractice the invention, and it is to be understood that otherembodiments may be utilized and that process or mechanical changes maybe made without departing from the scope of the present invention. Theterms wafer and substrate used in the following description include anybase semiconductor structure. Both are to be understood as includingsilicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI)technology, thin film transistor (TFT) technology, doped and undopedsemiconductors, epitaxial layers of a silicon supported by a basesemiconductor, as well as other semiconductor support structures wellknown to one skilled in the art. Furthermore, when reference is made toa wafer or substrate in the following description, previous processsteps may have been utilized to form regions/junctions in the basesemiconductor structure. The following detailed description is,therefore, not to be taken in a limiting sense, and the scope of thepresent invention is defined only by the appended claims.

[0037] Container Structures

[0038] In FIG. 1, after preparing a first support layer or, in thisembodiment, insulating layer 10 and a buried contact 15 on the surfaceof a substrate 5 using conventional processing, one or more holes 20 areformed in the insulating layer 10, exposing a portion of contact 15. Inthis embodiment, hole 20 is a container hole used in the formation of acontainer capacitor. Container hole 20 has sidewalls defined by thesurrounding insulating layer 10.

[0039] Container holes 20 are generally formed over active areas of thesubstrate 5 when forming a container structure for a capacitor in anintegrated circuit. The processing for forming insulating layer 10 onthe surface of substrate 5, as well as the processing for formingcontainer holes 20 in insulating layer 10, are not detailed herein assuch methods are well known to those of ordinary skill in the art.

[0040] A second support layer or, in this embodiment, container layer 30is then formed on substrate 5 and insulating layer 10 in FIG. 2.Container layer 30 is preferably hemispherical grain polysilicon (HSG)when used as a bottom plate of a capacitor. However, container layer 30may further include other materials, such as amorphous silicon andpolysilicon either singly or in combination. Similarly, insulating layer10 is preferably borophosphosilicate glass (BPSG) when container layer30 is used as a bottom plate of a capacitor, but insulating layer 10 mayinclude other insulative materials, such as oxides or nitrides.Container layer 30, when used as a bottom plate of a capacitor shouldfurther be conductively doped for conductivity at some stage in theprocessing. Such doping may occur at any stage such as concurrently withformation of container layer 30, after formation of container layer 30,after removal of unwanted material from container layer 30, or at someother processing stage.

[0041] Following deposition or formation of container layer 30, resistlayer 40 is formed overlying insulating layer 10 and container layer 30as shown in FIG. 3. Resist layer 40 is preferably spun on. Typicalthickness of resist layer 40 may be 0.5 to 1.5 μm. Resist layer 40contains a resist material that is light or energy sensitive, such thatresist material receiving exposure will have physical characteristicsdifferent from resist material not receiving exposure. Such resistmaterials are typically reactive to a specific set or range of energytypes, e.g., a specific set or range of wavelengths of light.

[0042] Resist layer 40 fills container holes 20 to protect them duringsubsequent processing. Resist layer 40 is preferably OIR-897-10Iphotoresist produced by Olin Corporation or PFI 66A7 photoresistproduced Sumitomo Chemical Co. LTD as used herein, although theinvention is applicable to all photoresist compositions andtechnologies.

[0043] In FIG. 4, resist layer 40 is exposed to electromagneticradiation or light waves 55, typically UV light, of a type capable ofexposing the resist material in resist layer 40. Resist layer 40contains photoresist material of a positive type, i.e., that which ismore easily removed, or more vulnerable to solvents, when exposed tolight or energy.

[0044] The duration and intensity of exposure to waves 55 should be of alevel such that the resultant exposed resist portion 70 extends tocontainer layer 30 on the surface of insulating layer 10, but such thatan underexposed resist portion 90 remains in container hole 20. Due tothe increased thickness of resist layer 40 above container hole 20,relative to the thickness overlying the surface of insulating layer 10,the duration and intensity of exposure to waves 55 can be controlled tosufficiently expose all of resist layer 40 overlying the surface ofinsulating layer 10 to permit removal of exposed resist portion 70 usingconventional washing techniques, yet leave portions of resist layer 40in container hole 20 insufficiently exposed to permit ready removal ofunderexposed resist portion 90 under similar conditions. The preferredexposure is between approximately 125 mJ and 200 mJ for the preferredresist materials. Adjustments to these preferred conditions will benecessary based on the thickness of resist layer 40 overlying thesurface of insulating layer 10, the type of positive photoresistmaterial chosen and the desired depth 130 of underexposed resist portion90.

[0045] In FIG. 5, exposed resist portion 70 is removed conventionally,leaving underexposed resist portion 90 in container hole 20. Uncoveredportions of container layer 30 are then removed in FIG. 6 without usingCMP. A wet poly etch may be used where container layer 30 is HSGpolysilicon. It is noted that the poly etch resulted in faster etchrates for doped HSG polysilicon than undoped HSG polysilicon. Splitsusing 2.25% TMAH [tetramethylammonium hydroxide, N(CH₃)₄OH] were used todrive the selectivity towards etching undoped HSG polysilicon fasterthan doped material. Other non-mechanical removal techniques may beused, such as alternative etch processes or chemical dissolution. It isnoted that non-mechanical processes offer an additional advantage overtraditional CMP removal of HSG polysilicon in that such non-mechanicalprocesses are capable of removing both surface HSG polysilicon andbackside HSG polysilicon simultaneously. CMP removal of surface HSGpolysilicon must be followed by a separate removal of backside CMP asexisting CMP processes are incapable of performing simultaneousplanarization of both sides of the wafer.

[0046] Further processing may be performed to produce a containercapacitor as shown in FIG. 7. The processing is well known and includesremoval of underexposed resist portion 90 to expose the inside of thecontainer, removal of a portion of insulating layer 10 to expose theoutside of the container, formation of a dielectric layer 260 andformation of a cell plate 270. Removal of underexposed resist portion 90may include such traditional methods such as using a hydrogen peroxideand sulfuric acid solution (“piranha etch” or “Carro's acid”).

[0047] In another embodiment, processing proceeds as shown in anddescribed with reference to FIGS. 1-3. Rather than adjusting intensityand duration of waves 55, waves 55 are directed at the surface at anincident angle 60 relative to the surface. By using an angled incidentto expose the resist, intensity and duration of waves 55 become lesscontrolling of the exposure as the waves 55 are not capable of exposingsome portions of resist layer 40 inside container hole 20. Substrate 5is preferably rotated about an axis generally perpendicular with thesurface during exposure. Such rotation produces a cone-like structure inunderexposed resist portion 90, such that exposed resist depth 80 onopposing sidewalls of container hole 20 are approximately equal. As analternative, the source of waves 55 could be rotated about the same axiswhile the substrate 5 remains stationary to produce substantiallysimilar results.

[0048] The incident angle 60 is adjusted to control the depth ofpenetration of the waves 55 into the container hole 20. A representativepenetrating wave 55A illustrates how a desired exposed resist depth 80is achieved for the container hole 20. Increasing the incident angle 60will increase the penetrating depth into the container hole and, thus,increase the amount of exposed resist in the container hole 20.

[0049] The penetration depth 80 can also be controlled by varying theangle 60 in conjunction with variation of the wavelength of the waves55. A larger wavelength will decrease penetration into the containerhole 20 at a given incident angle. Similarly, if the wavelength ismaintained, the penetration depth 80 can be increased by increasing theincident angle 60. Accordingly, both aspects can be variedsimultaneously to produce a desired resist exposure in the containerhole 20.

[0050] It should be recognized that because angle of incident has asignificant impact on penetration of waves 55 into container hole 20,the light source itself does not need to be a single wavelength source.Generally, the light source contains wavelengths within a spectral rangethat (a) are selective to the resist used, i.e., will produce thedesired reaction, and (b) will not penetrate the container at a givenangle. Additional wavelengths that are not selective to the resist maybe present, but need not be considered.

[0051] Remaining processing proceeds in like fashion to the precedingembodiment. Exposed resist portion 70 is removed as shown in FIG. 9.Uncovered portions of container layer 30 are removed as shown in FIG.10. And a container capacitor may be formed as shown in and describedwith reference to FIG. 7.

[0052] In still another embodiment, processing proceeds as shown in anddescribed with reference to FIGS. 1-3. Rather than adjusting intensityand duration of waves 55 as in FIG. 4, waves 210 are chosen to have awavelength 220 such that waves 210 are generally incapable ofpenetrating container hole 20. The absorption characteristics of theresist material can generally be described by the function:

Absorption=Amplitude*e ^(αd)

[0053] where:

[0054] Amplitude is the amplitude of the waves; and

[0055] d is the depth of the resist at which absorption is determined.

[0056] Further, α is generally described by the function:

α≅4πk/λ

[0057] where:

[0058] k is the absorption coefficient of the resist material; and

[0059] λ is the wavelength 220 of the waves 210.

[0060] Accordingly, increases in k or decreases in λ can be used tolimit the depth of penetration by reducing absorption to a level that istoo low to sufficiently expose the resist at the depths in containerhole 20 for a given intensity of waves 210. Increases in k areaccomplished by choosing a resist material having higher k values.Decreases in λ are accomplished by choosing an energy source emittingappropriate wavelengths.

[0061] It will be recognized that few light sources produce a singlewavelength. Accordingly, waves 210 may often contain wavelengths 220capable of penetrating container holes 20. However, it will berecognized that exposed resist portion 70 will receive exposure from allwaves 210 and that underexposed resist portion 90 will receive reducedexposure given that some waves 210 will be incapable of penetratingcontainer hole 20. Furthermore, resist layer 40 must be a positiveresist reactive to at least some of the waves 210 having a wavelength220. Where some waves 210 are both capable of penetrating container hole20 and of causing a reaction in resist layer 40, controlled intensityand duration of waves 210 should be used such that resist portion 90does not receive excessive exposure.

[0062] This embodiment may make use of photolithography technologycommonly thought of as outdated. As an example, G-line photolithographytechnology can be used in this type of processing as resist materialsfor this technology have a relatively high k value. G-line generallyrefers to the 436 nm wavelength produced by a mercury light source, andhas generally fallen out of service in photolithography due toresolution limitations caused by the relatively large wavelength.

[0063] Furthermore, in this embodiment it is the wavelength thatcontrols the depth of penetration into container hole 20. Thus, theangle of the light or energy source is not critical and an incoherentflood-type exposure may be employed. A benefit of using a flood typeexposure is that an entire wafer, or multiple wafers, can be exposed atonce, eliminating the necessity of expensive stepping technology andincreasing efficiency with resulting cost reduction. As one example,standard equipment used for bulk erasing of flash, typically a UVspectrum type of light source, can be used.

[0064] If a wavelength can interact and cause a change in the resist,then it must be of a size that generally prohibits interaction of theresist inside the container holes. If the wavelength does not cause achange in the resist, then it is unnecessary to filter it from the lightsource. Generally, the light source contains wavelengths within aspectral range that (a) are selective to the resist used and (b) willnot penetrate the container.

[0065] Upon exposure of resist layer 40, remaining processing proceedsin like fashion to the preceding embodiments. Exposed resist portion 70is removed then uncovered portions of container layer 30 are removed inlike fashion to that shown in and described with reference to FIGS. 5-6or 9-10. As in previous embodiments, a container capacitor may be formedas shown in and described with reference to

[0066]FIG. 7.

[0067] In a further embodiment, processing proceeds as shown in anddescribed with reference to FIGS. 1-3. Rather than adjusting intensityand duration of waves 55 as in FIG. 4, heat or other energy from anenergy source 190 is directed from below contact hole 20. The energysource 190 may utilize convective heat transfer or conductive heattransfer, or it may produce electromagnetic radiation or other radiatedenergy to be absorbed by the substrate 5. As shown in FIG. 12, waves 55representing the energy transfer are directed at substrate 5 from belowcontact hole 20. The increase in thermal energy due to the absorption ofwaves 55 by substrate 5 will be transferred by conduction towardcontainer hole 20. Resist layer 40 will absorb more thermal energy incontainer hole 20 than it will above the surface of insulating layer 10as the material in container hole 20 will have more surface area pervolume for accepting conductive energy transfer than material on thesurface, as well as less surface area per volume for dissipation ofabsorbed energy. Accordingly, material in container hole 20 will be at ahigher temperature than material at the surface until a steady state isreached. This differential of absorbed thermal energy and resultanttemperature differential in resist layer 40 can cause resist portion 95to harden more than resist portion 75, permitting the subsequent removalof resist portion 75 through conventional washing techniques whileleaving behind resist portion 95. It will be apparent that thisembodiment does not require the use of a photoresist material, but canmake use of any material that hardens or becomes more resistant towashing or dissolution through the absorption of thermal energy orincrease in temperature.

[0068] Upon hardening resist portion 95, remaining processing proceedsin like fashion to the preceding embodiments. Unhardened resist portion75 is removed then uncovered portions of container layer 30 are removedin like fashion to that shown in and described with reference to FIGS.5-6 or 9-10. As in previous embodiments, a container capacitor may beformed as shown in and described with reference to

[0069]FIG. 7.

[0070] In a still further embodiment, an insulating layer 10 and buriedcontact 15 are formed on a substrate 5 through conventional processingin FIG. 13. It will be trivial to those skilled in the art thatinsulating layer 10 will be formed in at least two layers in order toform buried contact 15 below the surface of insulating layer 10.Furthermore, first resist layer 40 is formed overlying insulating layer10. A reticle or mask 235 is used to define a future container hole.Waves 232 are directed toward the surface of first resist layer 40.Waves 232A are blocked by opaque regions 237 on mask 235 while waves232B are allowed to expose first resist layer 40. As shown and used inFIG. 13, first resist layer 40 is a positive photoresist.

[0071] Upon development and washing, first resist layer 40 becomespatterned in FIG. 14 to define a future container hole. In FIG. 15, aportion of insulating layer 10 exposed by patterned first resist layer40 is removed to define container hole 20, and first resist layer 40 issubsequently removed. In FIG. 16, container layer 30 is formed overlyinginsulating layer 10 and lining container hole 20. In FIG. 17, secondresist layer 45 is formed overlying insulating layer 10 and fillingcontainer hole 20. In this embodiment, second resist layer 45 is of anopposite type to first resist layer 40, i.e., second resist layer 45 isa negative photoresist in this embodiment. Accordingly, exposed areas ofsecond resist layer 45 are more resistant to removal than unexposedareas of the resist.

[0072] In FIG. 18, the same mask 235 is realigned with container hole 20and waves 232 are directed toward the surface of second resist layer 45creating exposed resist portion 97 and underexposed resist portion 77.As second resist layer 45 is a negative resist in this embodiment, upondevelopment and washing of the second resist layer 45, only exposedresist portion 97 remains, as shown in FIG. 19.

[0073] Remaining processing proceeds in like fashion to the precedingembodiments. Uncovered portions of container layer 30 are removed inlike fashion to that shown in and described with reference to FIGS. 5-6or 9-10, with the trivial exception that exposed resist portion 97extends above the sidewalls of container hole 20. As in previousembodiments, a container capacitor may be formed in like fashion asshown in and described with reference to FIG. 7.

[0074] It will be readily apparent to those skilled in the art thatsimilar results could be obtained in this embodiment using a negativephotoresist for first resist layer 40, with appropriate and obviousmodification to reticle 235, and a positive photoresist for secondresist layer 45.

[0075] Memory Cells

[0076]FIG. 20 depicts one embodiment of a container structure as used ina container capacitor for a memory cell. The container structure isformed over a contact 15 to an active area of substrate 5. Containerlayer 30 is formed between adjacent word lines 250, having structureswell understood in the art, and acts as the bottom plate of thecontainer capacitor.

[0077] Container layer 30 is covered by a dielectric layer 260.Container layer 30 is formed in accordance with the invention.Dielectric layer 260 is an insulative material. Dielectric layer 260 isfurther covered by cell plate 270. Cell plate 270 is preferablyconductively-doped polysilicon. Such memory cells are suitable for usein memory devices.

[0078] Memory Devices

[0079]FIG. 21 is a simplified block diagram of a memory device accordingto one embodiment of the invention. The memory device 300 includes anarray of memory cells 302, address decoder 304, row access circuitry306, column access circuitry 308, control circuitry 310, andInput/Output circuit 312. The memory can be coupled to an externalmicroprocessor 314, or memory controller for memory accessing. Thememory receives control signals from the processor 314, such as WE*,RAS* and CAS* signals. The memory is used to store data which isaccessed via I/O lines. It will be appreciated by those skilled in theart that additional circuitry and control signals can be provided, andthat the memory device of FIG. 21 has been simplified to help focus onthe invention. At least one of the memory cells has a containercapacitor of the invention.

[0080] It will be understood that the above description of a DRAM(Dynamic Random Access Memory) is intended to provide a generalunderstanding of the memory and is not a complete description of all theelements and features of a DRAM. Further, the invention is equallyapplicable to any size and type of memory circuit and is not intended tobe limited to the DRAM described above. Other alternative types ofdevices include SRAM (Static Random Access Memory) or Flash memories.Additionally, the DRAM could be a synchronous DRAM commonly referred toas SGRAM (Synchronous Graphics Random Access Memory), SDRAM (SynchronousDynamic Random Access Memory), SDRAM 11, and DDR SDRAM (Double Data RateSDRAM), as well as Synchlink or Rambus DRAMs.

[0081] As recognized by those skilled in the art, memory devices of thetype described herein are generally fabricated as an integrated circuitcontaining a variety of semiconductor devices. The integrated circuit issupported by a substrate. Integrated circuits are typically repeatedmultiple times on each substrate. The substrate is further processed toseparate the integrated circuits into dies as is well known in the art.

[0082] Semiconductor Dies

[0083] With reference to FIG. 22, in one embodiment, a semiconductor die710 is produced from a silicon wafer 700. A die is an individualpattern, typically rectangular, on a substrate that contains circuitry,or integrated circuit devices, to perform a specific function. At leastone of the integrated circuit devices is a container capacitor asdisclosed herein. A semiconductor wafer will typically contain arepeated pattern of such dies containing the same functionality. Die 710may contain circuitry for the inventive memory device, as discussedabove. Die 710 may further contain additional circuitry to extend tosuch complex devices as a monolithic processor with multiplefunctionality. Die 710 is typically packaged in a protective casing (notshown) with leads extending therefrom (not shown) providing access tothe circuitry of the die for unilateral or bilateral communication andcontrol.

[0084] Circuit Modules

[0085] As shown in FIG. 23, two or more dies 710 may be combined, withor without protective casing, into a circuit module 800 to enhance orextend the functionality of an individual die 710. Circuit module 800may be a combination of dies 710 representing a variety of functions, ora combination of dies 710 containing the same functionality. Someexamples of a circuit module include memory modules, device drivers,power modules, communication modems, processor modules andapplication-specific modules and may include multilayer, multichipmodules. Circuit module 800 may be a subcomponent of a variety ofelectronic systems, such as a clock, a television, a cell phone, apersonal computer, an automobile, an industrial control system, anaircraft and others. Circuit module 800 will have a variety of leads 810extending therefrom and coupled to the dies 710 providing unilateral orbilateral communication and control.

[0086]FIG. 24 shows one embodiment of a circuit module as memory module900. Memory module 900 generally depicts a Single Inline Memory Module(SIMM) or Dual Inline Memory Module (DIMM). A SIMM or DIMM is generallya printed circuit board (PCB) or other support containing a series ofmemory devices. While a SIMM will have a single in-line set of contactsor leads, a DIMM will have a set of leads on each side of the supportwith each set representing separate I/O signals. Memory module 900contains multiple memory devices 910 contained on support 915, thenumber depending upon the desired bus width and the desire for parity.Memory module 900 may contain memory devices 910 on both sides ofsupport 915. Memory module 900 accepts a command signal from an externalcontroller (not shown) on a command link 920 and provides for data inputand data output on data links 930. The command link 920 and data links930 are connected to leads 940 extending from the support 915. Leads 940are shown for conceptual purposes and are not limited to the positionsshown in FIG. 24.

[0087] Electronic Systems

[0088]FIG. 25 shows an electronic system 1000 containing one or morecircuit modules 800. Electronic system 1000 generally contains a userinterface 1010. User interface 1010 provides a user of the electronicsystem 1000 with some form of control or observation of the results ofthe electronic system 1000. Some examples of user interface 1010 includethe keyboard, pointing device, monitor and printer of a personalcomputer; the tuning dial, display and speakers of a radio; the ignitionswitch and gas pedal of an automobile; and the card reader, keypad,display and currency dispenser of an automated teller machine. Userinterface 1010 may further describe access ports provided to electronicsystem 1000. Access ports are used to connect an electronic system tothe more tangible user interface components previously exemplified. Oneor more of the circuit modules 800 may be a processor providing someform of manipulation, control or direction of inputs from or outputs touser interface 1010, or of other information either preprogrammed into,or otherwise provided to, electronic system 1000. As will be apparentfrom the lists of examples previously given, electronic system 1000 willoften contain certain mechanical components (not shown) in addition tocircuit modules 800 and user interface 1010. It will be appreciated thatthe one or more circuit modules 800 in electronic system 1000 can bereplaced by a single integrated circuit. Furthermore, electronic system1000 may be a subcomponent of a larger electronic system.

[0089]FIG. 26 shows one embodiment of an electronic system as memorysystem 1100. Memory system 1100 contains one or more memory modules 900and a memory controller 1110. Memory controller 1110 provides andcontrols a bidirectional interface between memory system 1100 and anexternal system bus 1120. Memory system 1100 accepts a command signalfrom the external bus 1120 and relays it to the one or more memorymodules 900 on a command link 1130. Memory system 1100 provides for datainput and data output between the one or more memory modules 900 andexternal system bus 1120 on data links 1140.

[0090]FIG. 27 shows a further embodiment of an electronic system as acomputer system 1200. Computer system 1200 contains a processor 1210 anda memory system 1100 housed in a computer unit 1205. Computer system1200 is but one example of an electronic system containing anotherelectronic system, i.e., memory system 1100, as a subcomponent. Computersystem 1200 optionally contains user interface components. Depicted inFIG. 27 are a keyboard 1220, a pointing device 1230, a monitor 1240, aprinter 1250 and a bulk storage device 1260. It will be appreciated thatother components are often associated with computer system 1200 such asmodems, device driver cards, additional storage devices, etc. It willfurther be appreciated that the processor 1210 and memory system 1100 ofcomputer system 1200 can be incorporated on a single integrated circuit.Such single package processing units reduce the communication timebetween the processor and the memory circuit.

CONCLUSION

[0091] Chemical-mechanical planarization (CMP) may inherently inducedefects in the manufacture of integrated circuits. Traditionalprocessing for forming container capacitors utilizes CMP. The inventionprovides methods of forming container capacitors without the need forCMP by providing localized masking of the container holes. Containercapacitors of the invention are devoid of CMP-induced variations anddefects. Such container capacitors are especially suited for use inmemory cells, and various apparatus incorporating such memory cells.

[0092] While the invention has been described and illustrated withrespect to forming container capacitors for a memory cell, it should beapparent that the same processing techniques can be used to form othercontainer capacitors for other applications as well as othercontainer-shaped structures.

[0093] Although specific embodiments have been illustrated and describedherein, it will be appreciated by those of ordinary skill in the artthat any arrangement which is calculated to achieve the same purpose maybe substituted for the specific embodiments shown. Many adaptations ofthe invention will be apparent to those of ordinary skill in the art.Accordingly, this application is intended to cover any adaptations orvariations of the invention. It is manifestly intended that thisinvention be limited only by the following claims and equivalentsthereof.

What is claimed is:
 1. A method of forming a semiconductor containerstructure, comprising: forming an insulating layer having a surface andoverlying a substrate; forming a container hole in the insulating layerand having a closed bottom, an open top and sidewalls extending betweenthe closed bottom and open top; forming a container layer at least onthe surface of the insulating layer and the sidewalls and closed bottomof the container hole; forming a resist layer overlying the containerlayer and filling the container hole, wherein the resist layer is of apositive resist type; selectively exposing the resist layer to energycapable of exposing the resist layer, thereby forming an exposed resistportion and an underexposed resist portion, wherein the underexposedresist portion fills at least a portion of the container hole; removingthe exposed resist portion, thereby forming an uncovered portion of thecontainer layer; and removing the uncovered portion of the containerlayer using a non-mechanical technique.
 2. The method of claim 1,wherein forming an insulating layer further comprises forming andinsulating layer of an insulating material selected from the groupconsisting of borophosphosilicate glass, oxides and nitrides.
 3. Themethod of claim 1, wherein forming a container layer further comprisesforming a container layer of hemispherical grain polysilicon.
 4. Themethod of claim 3, further comprising: conductively doping the containerlayer.
 5. The method of claim 1, wherein selectively exposing the resistlayer to energy capable of exposing the resist layer further comprisesexposing the resist layer to a controlled energy dosage sufficient toexpose a portion of the resist layer overlying the surface of theinsulating layer and insufficient to expose a portion of the resistlayer in the container hole.
 6. The method of claim 5, wherein exposingthe resist layer to a controlled energy dosage further comprisesexposing the resist layer to an energy dosage between about 125 mJ and200 mJ.
 7. The method of claim 1, wherein selectively exposing theresist layer to energy capable of exposing the resist layer furthercomprises exposing the resist layer to energy having an angled incidentto control a depth of penetration of the container hole.
 8. The methodof claim 7, wherein exposing the resist layer to energy having an angledincident further comprises exposing the resist layer to energy having anangled incident generally incapable of exposing at least some portion ofthe resist layer in the container hole.
 9. The method of claim 1,wherein selectively exposing the resist layer to energy capable ofexposing the resist layer further comprises exposing the resist layer toenergy having an angled incident while rotating the substrate about anaxis generally perpendicular to the surface of the insulating layer. 10.The method of claim 1, wherein selectively exposing the resist layer toenergy capable of exposing the resist layer further comprises exposingthe resist layer to energy from a source having an angled incident whilerotating the source about an axis generally perpendicular to the surfaceof the insulating layer.
 11. The method of claim 7, further comprisingvarying a wavelength of the energy to further control the depth ofpenetration.
 12. The method of claim 1, wherein selectively exposing theresist layer to energy capable of exposing the resist layer furthercomprises exposing the resist layer to energy having at least onewavelength generally incapable of penetrating the container hole. 13.The method of claim 1, wherein selectively exposing the resist layer toenergy capable of exposing the resist layer further comprises exposingthe resist layer to energy from an incoherent source having at least onewavelength generally incapable of penetrating the container hole. 14.The method of claim 1, wherein the processing proceeds in the orderpresented.
 15. The method of claim 1, wherein selectively exposing theresist layer to energy capable of exposing the resist layer furthercomprises exposing the resist layer to energy generally incapable ofexposing the resist layer.
 16. The method of claim 1, wherein removingthe uncovered portion of the container layer using a non-mechanicaltechnique further comprises removing the uncovered portion of thecontainer layer using a non-mechanical technique selected from the groupconsisting of wet etch, etch and chemical dissolution.
 17. A method offorming a semiconductor container structure, comprising: forming aninsulating layer having a surface and overlying a substrate; defining acontainer hole in the insulating layer and having a closed bottom, anopen top and sidewalls extending between the closed bottom and open top;forming a container layer at least on the surface of the insulatinglayer and the sidewalls and closed bottom of the container hole; forminga resist layer overlying the container layer and filling the containerhole; exposing the substrate to energy capable of hardening the resistlayer, thereby forming a hardened resist portion and an unhardenedresist portion, wherein the hardened resist portion fills at least aportion of the container hole; removing the unhardened resist portion,thereby forming an uncovered portion of the container layer; andremoving the uncovered portion of the container layer using anon-mechanical technique.
 18. The method of claim 17, wherein exposingthe substrate to energy capable of hardening the resist layer furthercomprises exposing the substrate to thermal energy by a transfer methodselected from the group consisting of conductive heat transfer andconvective heat transfer.
 19. The method of claim 17, wherein exposingthe substrate to energy capable of hardening the resist layer furthercomprises absorbing radiated energy by the substrate.
 20. The method ofclaim 17, wherein removing the uncovered portion of the container layerusing a non-mechanical technique further comprises removing theuncovered portion of the container layer using a non-mechanicaltechnique selected from the group consisting of wet etch, etch andchemical dissolution.
 21. The method of claim 17, wherein the processingproceeds in the order presented.
 22. A method of forming a semiconductorcontainer structure, comprising: forming an insulating layer having asurface and overlying a substrate; forming a first resist layeroverlying the insulating layer, wherein the first resist layer is of afirst resist type; patterning the first resist layer using a reticle todefine a future container hole; forming the container hole in theinsulating layer and having a closed bottom, an open top and sidewallsextending between the closed bottom and open top; forming a containerlayer at least on the surface of the insulating layer and the sidewallsand closed bottom of the container hole; forming a second resist layeroverlying the container layer and filling the container hole, whereinthe second resist layer is of a second resist type, further wherein thesecond resist type is opposite the first resist type; patterning thesecond resist layer using the reticle, thereby forming a hardened resistportion and an unhardened resist portion, wherein the hardened resistportion fills the container hole; removing the unhardened resistportion, thereby forming an uncovered portion of the container layer;and removing the uncovered portion of the container layer using anon-mechanical technique.
 23. The method of claim 22, wherein forming afirst resist layer further comprises forming a first resist layer ofpositive resist material, further wherein forming a second resist layerfurther comprises forming a second resist layer of negative resistmaterial.
 24. The method of claim 22, wherein removing the uncoveredportion of the container layer using a non-mechanical technique furthercomprises removing the uncovered portion of the container layer using anon-mechanical technique selected from the group consisting of wet etch,etch and chemical dissolution.
 25. The method of claim 22, wherein theprocessing proceeds in the order presented.
 26. A container capacitor,comprising: a bottom plate having a closed bottom and sidewallsextending upward from the closed bottom, wherein the bottom plate isformed by a method comprising: forming an insulating layer having asurface and overlying a substrate, wherein the insulating layercomprises an insulating material selected from the group consisting ofborophosphosilicate glass, oxides and nitrides; forming a container holein the insulating layer and having a closed bottom, an open top andsidewalls extending between the closed bottom and open top; forming acontainer layer at least on the surface of the insulating layer and thesidewalls and closed bottom of the container hole, wherein the containerlayer comprises hemispherical grain polysilicon; forming a resist layeroverlying the container layer and filling the container hole, whereinthe resist layer is of a positive resist type; selectively exposing theresist layer to energy capable of exposing the resist layer, therebyforming an exposed resist portion and an underexposed resist portion,wherein the underexposed resist portion fills at least a portion of thecontainer hole; removing the exposed resist portion, thereby forming anuncovered portion of the container layer; removing the uncovered portionof the container layer using a non-mechanical technique selected fromthe group consisting of wet etch, etch and chemical dissolution, therebyforming the bottom plate; and removing the underexposed resist portion;a dielectric layer on the bottom plate; and a cell plate on thedielectric layer, wherein the dielectric layer is interposed between thecell plate and the bottom plate.
 27. A container capacitor, comprising:a bottom plate having a closed bottom and sidewalls extending upwardfrom the closed bottom, wherein the bottom plate is formed by a methodcomprising: forming an insulating layer having a surface and overlying asubstrate, wherein the insulating layer comprises an insulating materialselected from the group consisting of borophosphosilicate glass, oxidesand nitrides; forming a container hole in the insulating layer andhaving a closed bottom, an open top and sidewalls extending between theclosed bottom and open top; forming a container layer at least on thesurface of the insulating layer and the sidewalls and closed bottom ofthe container hole, wherein the container layer comprises hemisphericalgrain polysilicon; forming a resist layer overlying the container layerand filling the container hole, wherein the resist layer is of apositive resist type; selectively exposing the resist layer to energycapable of exposing the resist layer and at a controlled energy dosagesufficient to expose a portion of the resist layer overlying the surfaceof the insulating layer and insufficient to expose a portion of theresist layer in the container hole, thereby forming an exposed resistportion and an underexposed resist portion, wherein the underexposedresist portion fills at least a portion of the container hole; removingthe exposed resist portion, thereby forming an uncovered portion of thecontainer layer; removing the uncovered portion of the container layerusing a non-mechanical technique selected from the group consisting ofwet etch, etch and chemical dissolution, thereby forming the bottomplate; and removing the underexposed resist portion; a dielectric layeron the bottom plate; and a cell plate on the dielectric layer, whereinthe dielectric layer is interposed between the cell plate and the bottomplate.
 28. A container capacitor, comprising: a bottom plate having aclosed bottom and sidewalls extending upward from the closed bottom,wherein the bottom plate is formed by a method comprising: forming aninsulating layer having a surface and overlying a substrate, wherein theinsulating layer comprises an insulating material selected from thegroup consisting of borophosphosilicate glass, oxides and nitrides;forming a container hole in the insulating layer and having a closedbottom, an open top and sidewalls extending between the closed bottomand open top; forming a container layer at least on the surface of theinsulating layer and the sidewalls and closed bottom of the containerhole, wherein the container layer comprises hemispherical grainpolysilicon; forming a resist layer overlying the container layer andfilling the container hole, wherein the resist layer is of a positiveresist type; selectively exposing the resist layer to energy capable ofexposing the resist layer and having an angled incident to control adepth of penetration of the container hole, thereby forming an exposedresist portion and an underexposed resist portion, wherein theunderexposed resist portion fills at least a portion of the containerhole; removing the exposed resist portion, thereby forming an uncoveredportion of the container layer; removing the uncovered portion of thecontainer layer using a non-mechanical technique selected from the groupconsisting of wet etch, etch and chemical dissolution, thereby formingthe bottom plate; and removing the underexposed resist portion; adielectric layer on the bottom plate; and a cell plate on the dielectriclayer, wherein the dielectric layer is interposed between the cell plateand the bottom plate.
 29. A container capacitor, comprising: a bottomplate having a closed bottom and sidewalls extending upward from theclosed bottom, wherein the bottom plate is formed by a methodcomprising: forming an insulating layer having a surface and overlying asubstrate, wherein the insulating layer comprises an insulating materialselected from the group consisting of borophosphosilicate glass, oxidesand nitrides; forming a container hole in the insulating layer andhaving a closed bottom, an open top and sidewalls extending between theclosed bottom and open top; forming a container layer at least on thesurface of the insulating layer and the sidewalls and closed bottom ofthe container hole, wherein the container layer comprises hemisphericalgrain polysilicon; forming a resist layer overlying the container layerand filling the container hole, wherein the resist layer is of apositive resist type; selectively exposing the resist layer to energycapable of exposing the resist layer and having at least one wavelengthgenerally incapable of penetrating the container hole, thereby formingan exposed resist portion and an underexposed resist portion, whereinthe underexposed resist portion fills at least a portion of thecontainer hole; removing the exposed resist portion, thereby forming anuncovered portion of the container layer; removing the uncovered portionof the container layer using a non-mechanical technique selected fromthe group consisting of wet etch, etch and chemical dissolution, therebyforming the bottom plate; and removing the underexposed resist portion;a dielectric layer on the bottom plate; and a cell plate on thedielectric layer, wherein the dielectric layer is interposed between thecell plate and the bottom plate.
 30. A container capacitor, comprising:a bottom plate having a closed bottom and sidewalls extending upwardfrom the closed bottom, wherein the bottom plate is formed by a methodcomprising: forming an insulating layer having a surface and overlying asubstrate, wherein the insulating layer comprises an insulating materialselected from the group consisting of borophosphosilicate glass, oxidesand nitrides; forming a container hole in the insulating layer andhaving a closed bottom, an open top and sidewalls extending between theclosed bottom and open top; forming a container layer at least on thesurface of the insulating layer and the sidewalls and closed bottom ofthe container hole, wherein the container layer comprises hemisphericalgrain polysilicon; forming a resist layer overlying the container layerand filling the container hole, wherein the resist layer is of apositive resist type; exposing the substrate to energy capable ofhardening the resist layer, thereby forming a hardened resist portionand an unhardened resist portion, wherein the hardened resist portionfills at least a portion of the container hole; removing the unhardenedresist portion, thereby forming an uncovered portion of the containerlayer; removing the uncovered portion of the container layer using anon-mechanical technique selected from the group consisting of wet etch,etch and chemical dissolution, thereby forming the bottom plate; andremoving the underexposed resist portion; a dielectric layer on thebottom plate; and a cell plate on the dielectric layer, wherein thedielectric layer is interposed between the cell plate and the bottomplate.
 31. A container capacitor, comprising: a bottom plate having aclosed bottom and sidewalls extending upward from the closed bottom,wherein the bottom plate is formed by a method comprising: forming aninsulating layer having a surface and overlying a substrate, wherein theinsulating layer comprises an insulating material selected from thegroup consisting of borophosphosilicate glass, oxides and nitrides;forming a first resist layer overlying the insulating layer, wherein thefirst resist layer is of a first resist type; patterning the firstresist layer using a reticle to define a future container hole; formingthe container hole in the insulating layer and having a closed bottom,an open top and sidewalls extending between the closed bottom and opentop; forming a container layer at least on the surface of the insulatinglayer and the sidewalls and closed bottom of the container hole, whereinthe container layer comprises hemispherical grain polysilicon; forming asecond resist layer overlying the container layer and filling thecontainer hole, wherein the second resist layer is of a second resisttype, further wherein the second resist type is opposite the firstresist type; patterning the second resist layer using the reticle,thereby forming a hardened resist portion and an unhardened resistportion, wherein the hardened resist portion fills the container hole;removing the unhardened resist portion, thereby forming an uncoveredportion of the container layer; and removing the uncovered portion ofthe container layer using a non-mechanical technique selected from thegroup consisting of wet etch, etch and chemical dissolution, therebyforming the bottom plate; and removing the hardened resist portion; adielectric layer on the bottom plate; and a cell plate on the dielectriclayer, wherein the dielectric layer is interposed between the cell plateand the bottom plate.
 32. A semiconductor die, comprising: an integratedcircuit supported by a substrate and having a plurality of integratedcircuit devices, wherein at least one of the plurality of integratedcircuit devices is a container capacitor, the container capacitorcomprising: a bottom plate having a closed bottom and sidewallsextending upward from the closed bottom, wherein the bottom plate isformed by a method comprising: forming an insulating layer having asurface and overlying a substrate, wherein the insulating layercomprises an insulating material selected from the group consisting ofborophosphosilicate glass, oxides and nitrides; forming a container holein the insulating layer and having a closed bottom, an open top andsidewalls extending between the closed bottom and open top; forming acontainer layer at least on the surface of the insulating layer and thesidewalls and closed bottom of the container hole, wherein the containerlayer comprises hemispherical grain polysilicon; forming a resist layeroverlying the container layer and filling the container hole, whereinthe resist layer is of a positive resist type; selectively exposing theresist layer to energy capable of exposing the resist layer, therebyforming an exposed resist portion and an underexposed resist portion,wherein the underexposed resist portion fills at least a portion of thecontainer hole; removing the exposed resist portion, thereby forming anuncovered portion of the container layer; removing the uncovered portionof the container layer using a non-mechanical technique selected fromthe group consisting of wet etch, etch and chemical dissolution, therebyforming the bottom plate; and removing the underexposed resist portion;a dielectric layer on the bottom plate; and a cell plate on thedielectric layer, wherein the dielectric layer is interposed between thecell plate and the bottom plate.
 33. A semiconductor die, comprising: anintegrated circuit supported by a substrate and having a plurality ofintegrated circuit devices, wherein at least one of the plurality ofintegrated circuit devices is a container capacitor, the containercapacitor comprising: a bottom plate having a closed bottom andsidewalls extending upward from the closed bottom, wherein the bottomplate is formed by a method comprising: forming an insulating layerhaving a surface and overlying a substrate, wherein the insulating layercomprises an insulating material selected from the group consisting ofborophosphosilicate glass, oxides and nitrides; forming a container holein the insulating layer and having a closed bottom, an open top andsidewalls extending between the closed bottom and open top; forming acontainer layer at least on the surface of the insulating layer and thesidewalls and closed bottom of the container hole, wherein the containerlayer comprises hemispherical grain polysilicon; forming a resist layeroverlying the container layer and filling the container hole, whereinthe resist layer is of a positive resist type; exposing the substrate toenergy capable of hardening the resist layer, thereby forming a hardenedresist portion and an unhardened resist portion, wherein the hardenedresist portion fills at least a portion of the container hole; removingthe unhardened resist portion, thereby forming an uncovered portion ofthe container layer; removing the uncovered portion of the containerlayer using a non-mechanical technique selected from the groupconsisting of wet etch, etch and chemical dissolution, thereby formingthe bottom plate; and removing the underexposed resist portion; adielectric layer on the bottom plate; and a cell plate on the dielectriclayer, wherein the dielectric layer is interposed between the cell plateand the bottom plate.
 34. A semiconductor die, comprising: an integratedcircuit supported by a substrate and having a plurality of integratedcircuit devices, wherein at least one of the plurality of integratedcircuit devices is a container capacitor, the container capacitorcomprising: a bottom plate having a closed bottom and sidewallsextending upward from the closed bottom, wherein the bottom plate isformed by a method comprising: forming an insulating layer having asurface and overlying a substrate, wherein the insulating layercomprises an insulating material selected from the group consisting ofborophosphosilicate glass, oxides and nitrides; forming a first resistlayer overlying the insulating layer, wherein the first resist layer isof a first resist type; patterning the first resist layer using areticle to define a future container hole; forming the container hole inthe insulating layer and having a closed bottom, an open top andsidewalls extending between the closed bottom and open top; forming acontainer layer at least on the surface of the insulating layer and thesidewalls and closed bottom of the container hole, wherein the containerlayer comprises hemispherical grain polysilicon; forming a second resistlayer overlying the container layer and filling the container hole,wherein the second resist layer is of a second resist type, furtherwherein the second resist type is opposite the first resist type;patterning the second resist layer using the reticle, thereby forming ahardened resist portion and an unhardened resist portion, wherein thehardened resist portion fills the container hole; removing theunhardened resist portion, thereby forming an uncovered portion of thecontainer layer; and removing the uncovered portion of the containerlayer using a non-mechanical technique selected from the groupconsisting of wet etch, etch and chemical dissolution, thereby formingthe bottom plate; and removing the hardened resist portion; a dielectriclayer on the bottom plate; and a cell plate on the dielectric layer,wherein the dielectric layer is interposed between the cell plate andthe bottom plate.
 35. A memory device, comprising: an array of memorycells, wherein at least one memory cell has a container capacitor, thecontainer capacitor comprising: a bottom plate having a closed bottomand sidewalls extending upward from the closed bottom, wherein thebottom plate is formed by a method comprising: forming an insulatinglayer having a surface and overlying a substrate, wherein the insulatinglayer comprises an insulating material selected from the groupconsisting of borophosphosilicate glass, oxides and nitrides; forming acontainer hole in the insulating layer and having a closed bottom, anopen top and sidewalls extending between the closed bottom and open top;forming a container layer at least on the surface of the insulatinglayer and the sidewalls and closed bottom of the container hole, whereinthe container layer comprises hemispherical grain polysilicon; forming aresist layer overlying the container layer and filling the containerhole, wherein the resist layer is of a positive resist type; selectivelyexposing the resist layer to energy capable of exposing the resistlayer, thereby forming an exposed resist portion and an underexposedresist portion, wherein the underexposed resist portion fills at least aportion of the container hole; removing the exposed resist portion,thereby forming an uncovered portion of the container layer; removingthe uncovered portion of the container layer using a non-mechanicaltechnique selected from the group consisting of wet etch, etch andchemical dissolution, thereby forming the bottom plate; and removing theunderexposed resist portion; a dielectric layer on the bottom plate; anda cell plate on the dielectric layer, wherein the dielectric layer isinterposed between the cell plate and the bottom plate; a row accesscircuit coupled to the array of memory cells; a column access circuitcoupled to the array of memory cells; and an address decoder circuitcoupled to the row access circuit and the column access circuit.
 36. Amemory device, comprising: an array of memory cells, wherein at leastone memory cell has a container capacitor, the container capacitorcomprising: a bottom plate having a closed bottom and sidewallsextending upward from the closed bottom, wherein the bottom plate isformed by a method comprising: forming an insulating layer having asurface and overlying a substrate, wherein the insulating layercomprises an insulating material selected from the group consisting ofborophosphosilicate glass, oxides and nitrides; forming a container holein the insulating layer and having a closed bottom, an open top andsidewalls extending between the closed bottom and open top; forming acontainer layer at least on the surface of the insulating layer and thesidewalls and closed bottom of the container hole, wherein the containerlayer comprises hemispherical grain polysilicon; forming a resist layeroverlying the container layer and filling the container hole, whereinthe resist layer is of a positive resist type; exposing the substrate toenergy capable of hardening the resist layer, thereby forming a hardenedresist portion and an unhardened resist portion, wherein the hardenedresist portion fills at least a portion of the container hole; removingthe unhardened resist portion, thereby forming an uncovered portion ofthe container layer; removing the uncovered portion of the containerlayer using a non-mechanical technique selected from the groupconsisting of wet etch, etch and chemical dissolution, thereby formingthe bottom plate; and removing the underexposed resist portion; adielectric layer on the bottom plate; and a cell plate on the dielectriclayer, wherein the dielectric layer is interposed between the cell plateand the bottom plate; a row access circuit coupled to the array ofmemory cells; a column access circuit coupled to the array of memorycells; and an address decoder circuit coupled to the row access circuitand the column access circuit.
 37. A memory device, comprising: an arrayof memory cells, wherein at least one memory cell has a containercapacitor, the container capacitor comprising: a bottom plate having aclosed bottom and sidewalls extending upward from the closed bottom,wherein the bottom plate is formed by a method comprising: forming aninsulating layer having a surface and overlying a substrate, wherein theinsulating layer comprises an insulating material selected from thegroup consisting of borophosphosilicate glass, oxides and nitrides;forming a first resist layer overlying the insulating layer, wherein thefirst resist layer is of a first resist type; patterning the firstresist layer using a reticle to define a future container hole; formingthe container hole in the insulating layer and having a closed bottom,an open top and sidewalls extending between the closed bottom and opentop; forming a container layer at least on the surface of the insulatinglayer and the sidewalls and closed bottom of the container hole, whereinthe container layer comprises hemispherical grain polysilicon; forming asecond resist layer overlying the container layer and filling thecontainer hole, wherein the second resist layer is of a second resisttype, further wherein the second resist type is opposite the firstresist type; patterning the second resist layer using the reticle,thereby forming a hardened resist portion and an unhardened resistportion, wherein the hardened resist portion fills the container hole;removing the unhardened resist portion, thereby forming an uncoveredportion of the container layer; and removing the uncovered portion ofthe container layer using a non-mechanical technique selected from thegroup consisting of wet etch, etch and chemical dissolution, therebyforming the bottom plate; and removing the hardened resist portion; adielectric layer on the bottom plate; and a cell plate on the dielectriclayer, wherein the dielectric layer is interposed between the cell plateand the bottom plate; a row access circuit coupled to the array ofmemory cells; a column access circuit coupled to the array of memorycells; and an address decoder circuit coupled to the row access circuitand the column access circuit.
 38. An electronic system, comprising: aprocessor; and a circuit module having a plurality of leads coupled tothe processor, and further having a semiconductor die coupled to theplurality of leads, wherein the semiconductor die comprises: anintegrated circuit supported by a substrate and having a plurality ofintegrated circuit devices, wherein at least one of the plurality ofintegrated circuit devices is a container capacitor, the containercapacitor comprising: a bottom plate having a closed bottom andsidewalls extending upward from the closed bottom, wherein the bottomplate is formed by a method comprising: forming an insulating layerhaving a surface and overlying a substrate, wherein the insulating layercomprises an insulating material selected from the group consisting ofborophosphosilicate glass, oxides and nitrides; forming a container holein the insulating layer and having a closed bottom, an open top andsidewalls extending between the closed bottom and open top; forming acontainer layer at least on the surface of the insulating layer and thesidewalls and closed bottom of the container hole, wherein the containerlayer comprises hemispherical grain polysilicon; forming a resist layeroverlying the container layer and filling the container hole, whereinthe resist layer is of a positive resist type; selectively exposing theresist layer to energy capable of exposing the resist layer, therebyforming an exposed resist portion and an underexposed resist portion,wherein the underexposed resist portion fills at least a portion of thecontainer hole; removing the exposed resist portion, thereby forming anuncovered portion of the container layer; removing the uncovered portionof the container layer using a non-mechanical technique selected fromthe group consisting of wet etch, etch and chemical dissolution, therebyforming the bottom plate; and removing the underexposed resist portion;a dielectric layer on the bottom plate; and a cell plate on thedielectric layer, wherein the dielectric layer is interposed between thecell plate and the bottom plate.
 39. An electronic system, comprising: aprocessor; and a circuit module having a plurality of leads coupled tothe processor, and further having a semiconductor die coupled to theplurality of leads, wherein the semiconductor die comprises: anintegrated circuit supported by a substrate and having a plurality ofintegrated circuit devices, wherein at least one of the plurality ofintegrated circuit devices is a container capacitor, the containercapacitor comprising: a bottom plate having a closed bottom andsidewalls extending upward from the closed bottom, wherein the bottomplate is formed by a method comprising: forming an insulating layerhaving a surface and overlying a substrate, wherein the insulating layercomprises an insulating material selected from the group consisting ofborophosphosilicate glass, oxides and nitrides; forming a container holein the insulating layer and having a closed bottom, an open top andsidewalls extending between the closed bottom and open top; forming acontainer layer at least on the surface of the insulating layer and thesidewalls and closed bottom of the container hole, wherein the containerlayer comprises hemispherical grain polysilicon; forming a resist layeroverlying the container layer and filling the container hole, whereinthe resist layer is of a positive resist type; exposing the substrate toenergy capable of hardening the resist layer, thereby forming a hardenedresist portion and an unhardened resist portion, wherein the hardenedresist portion fills at least a portion of the container hole; removingthe unhardened resist portion, thereby forming an uncovered portion ofthe container layer; removing the uncovered portion of the containerlayer using a non-mechanical technique selected from the groupconsisting of wet etch, etch and chemical dissolution, thereby formingthe bottom plate; and removing the underexposed resist portion; adielectric layer on the bottom plate; and a cell plate on the dielectriclayer, wherein the dielectric layer is interposed between the cell plateand the bottom plate.
 40. An electronic system, comprising: a processor;and a circuit module having a plurality of leads coupled to theprocessor, and further having a semiconductor die coupled to theplurality of leads, wherein the semiconductor die comprises: anintegrated circuit supported by a substrate and having a plurality ofintegrated circuit devices, wherein at least one of the plurality ofintegrated circuit devices is a container capacitor, the containercapacitor comprising: a bottom plate having a closed bottom andsidewalls extending upward from the closed bottom, wherein the bottomplate is formed by a method comprising: forming an insulating layerhaving a surface and overlying a substrate, wherein the insulating layercomprises an insulating material selected from the group consisting ofborophosphosilicate glass, oxides and nitrides; forming a first resistlayer overlying the insulating layer, wherein the first resist layer isof a first resist type; patterning the first resist layer using areticle to define a future container hole; forming the container hole inthe insulating layer and having a closed bottom, an open top andsidewalls extending between the closed bottom and open top; forming acontainer layer at least on the surface of the insulating layer and thesidewalls and closed bottom of the container hole, wherein the containerlayer comprises hemispherical grain polysilicon; forming a second resistlayer overlying the container layer and filling the container hole,wherein the second resist layer is of a second resist type, furtherwherein the second resist type is opposite the first resist type;patterning the second resist layer using the reticle, thereby forming ahardened resist portion and an unhardened resist portion, wherein thehardened resist portion fills the container hole; removing theunhardened resist portion, thereby forming an uncovered portion of thecontainer layer; and removing the uncovered portion of the containerlayer using a non-mechanical technique selected from the groupconsisting of wet etch, etch and chemical dissolution, thereby formingthe bottom plate; and removing the hardened resist portion; a dielectriclayer on the bottom plate; and a cell plate on the dielectric layer,wherein the dielectric layer is interposed between the cell plate andthe bottom plate.
 41. A container capacitor, comprising: a bottom platehaving a closed bottom and sidewalls extending upward from the closedbottom, wherein the bottom plate is a portion of a hemispherical grainpolysilicon layer formed by a blanket deposition process and wherein thebottom plate is devoid of mechanical planarization effects; a dielectriclayer on the bottom plate; and a cell plate on the dielectric layer,wherein the dielectric layer is interposed between the cell plate andthe bottom plate.
 42. A method of localized masking of holes,comprising: forming a first support layer having a surface; forming ahole in the first support layer and having a closed bottom, an open topand sidewalls extending between the closed bottom and open top; forminga resist layer overlying the first support layer and filling the hole,wherein the resist layer is of a positive resist type; selectivelyexposing the resist layer to energy capable of exposing the resistlayer, thereby forming an exposed resist portion and an underexposedresist portion, wherein the underexposed resist portion fills at least aportion of the hole; and removing the exposed resist portion.
 43. Themethod of claim 42, further comprising: forming a second support layerinterposed between the first support layer and the resist layer;uncovering a portion of the second support layer by removing the exposedresist portion, thereby forming an uncovered portion of the secondsupport layer; and removing the uncovered portion of the second supportlayer using a non-mechanical technique selected from the groupconsisting of wet etch, etch and chemical dissolution.
 44. The method ofclaim 42, wherein selectively exposing the resist layer to energycapable of exposing the resist layer further comprises exposing theresist layer to a controlled energy dosage sufficient to expose aportion of the resist layer overlying the surface of the first supportlayer and insufficient to expose a portion of the resist layer in thehole.
 45. The method of claim 44, wherein exposing the resist layer to acontrolled energy dosage further comprises exposing the resist layer toan energy dosage between about 125 mJ and 200 mJ.
 46. The method ofclaim 42, wherein selectively exposing the resist layer to energycapable of exposing the resist layer further comprises exposing theresist layer to energy having an angled incident to control a depth ofpenetration of the hole.
 47. The method of claim 46, wherein exposingthe resist layer to energy having an angled incident further comprisesexposing the resist layer to energy having an angled incident generallyincapable of exposing at least some portion of the resist layer in thehole.
 48. The method of claim 42, wherein selectively exposing theresist layer to energy capable of exposing the resist layer furthercomprises exposing the resist layer to energy having an angled incidentwhile rotating the substrate about an axis generally perpendicular tothe surface of the first support layer.
 49. The method of claim 42,wherein selectively exposing the resist layer to energy capable ofexposing the resist layer further comprises exposing the resist layer toenergy from a source having an angled incident while rotating the sourceabout an axis generally perpendicular to the surface of the firstsupport layer.
 50. The method of claim 46, further comprising varying awavelength of the energy to further control the depth of penetration.51. The method of claim 42, wherein selectively exposing the resistlayer to energy capable of exposing the resist layer further comprisesexposing the resist layer to energy having at least one wavelengthgenerally incapable of penetrating the hole.
 52. The method of claim 42,wherein selectively exposing the resist layer to energy capable ofexposing the resist layer further comprises exposing the resist layer toenergy from an incoherent source having at least one wavelengthgenerally incapable of penetrating the hole.
 53. The method of claim 42,wherein the processing proceeds in the order presented.
 54. The methodof claim 42, wherein selectively exposing the resist layer to energycapable of exposing the resist layer further comprises exposing theresist layer to energy generally incapable of exposing the resist layer.55. A method of localized masking of holes, comprising: forming a firstsupport layer having a surface; defining a hole in the first supportlayer and having a closed bottom, an open top and sidewalls extendingbetween the closed bottom and open top; forming a resist layer overlyingthe first support layer and filling the hole, wherein the resist layeris of a positive resist type; exposing the first support layer to energycapable of hardening the resist layer, thereby forming a hardened resistportion and an unhardened resist portion, wherein the hardened resistportion fills at least a portion of the hole; and removing theunhardened resist portion.
 56. The method of claim 55, furthercomprising: forming a second support layer interposed between the firstsupport layer and the resist layer; uncovering a portion of the secondsupport layer by removing the unhardened resist portion, thereby formingan uncovered portion of the second support layer; and removing theuncovered portion of the second support layer using a non-mechanicaltechnique selected from the group consisting of wet etch, etch andchemical dissolution.
 57. The method of claim 55, wherein exposing thefirst support layer to energy capable of hardening the resist layerfurther comprises exposing the first support layer to thermal energy bya transfer method selected from the group consisting of conductive heattransfer and convective heat transfer.
 58. The method of claim 55,wherein exposing the first support layer to energy capable of hardeningthe resist layer further comprises absorbing radiated energy by thefirst support layer.
 59. The method of claim 55, wherein the processingproceeds in the order presented.
 60. A method of localized masking ofholes, comprising: forming a first support layer having a surface;forming a first resist layer overlying the first support layer, whereinthe first resist layer is of a first resist type; patterning the firstresist layer using a reticle to define a future hole; forming the holein the first support layer and having a closed bottom, an open top andsidewalls extending between the closed bottom and open top; forming asecond resist layer overlying the first support layer and filling thehole, wherein the second resist layer is of a second resist type,further wherein the second resist type is opposite the first resisttype; patterning the second resist layer using the reticle, therebyforming a hardened resist portion and an unhardened resist portion,wherein the hardened resist portion fills the hole; and removing theunhardened resist portion.
 61. The method of claim 60, furthercomprising: forming a second support layer interposed between the firstsupport layer and the second resist layer; uncovering a portion of thesecond support layer by removing the unhardened resist portion, therebyforming an uncovered portion of the second support layer; and removingthe uncovered portion of the second support layer using a non-mechanicaltechnique selected from the group consisting of wet etch, etch andchemical dissolution.
 62. The method of claim 60, wherein forming afirst resist layer further comprises forming a first resist layer ofpositive resist material, further wherein forming a second resist layerfurther comprises forming a second resist layer of negative resistmaterial.
 63. The method of claim 60, wherein the processing proceeds inthe order presented.
 64. The container capacitor according to claim 26,wherein the energy for exposing the resist layer is between about 125 mJand 200 mJ.
 65. The container capacitor according to claim 27, whereinthe energy for exposing the resist layer is between about 125 mJ and 200mJ.
 66. The container capacitor according to claim 28, wherein theenergy for exposing the resist layer is between about 125 mJ and 200 mJ.67. A processing stage integrated circuit structure, comprising: asubstrate; an insulating layer on the substrate; a container hole in theinsulating layer having a closed bottom, an open top and sidewallsextending between the closed bottom and open top; a container layer onthe sidewalls and closed bottom of the container hole; and anunder-exposed, positive-type resist layer in the container hole coveringa portion of the container layer, wherein a surface of the resist layeropen to the open top is non-planar.
 68. The structure of claim 67,wherein the container layer includes hemispherical grain polysilicon.69. The structure of claim 67, wherein the container layer isconductively doped.
 70. The structure of claim 67, wherein the containerlayer is on the insulating layer.
 71. The structure of claim 67, whereinan exposed, positive-type resist layer extends over the container layerand the under-exposed, positive-type resist layer.
 72. The structure ofclaim 67, wherein the surface of the resist layer is concave.
 73. Thestructure of claim 67, wherein the surface of the resist layer isconvex.
 74. The structure of claim 67, wherein the resist layer isadapted to be removed to expose the container layer.
 75. A processingstage integrated circuit structure, comprising: a substrate; aninsulating layer on the substrate; a container hole in the insulatinglayer having a closed bottom, an open top and sidewalls extendingbetween the closed bottom and open top; a container layer on thesidewalls and closed bottom of the container hole; and an under-exposed,positive-type resist layer in the container hole covering a portion ofthe container layer, wherein a surface of the resist layer at the opentop has a cone-like structure.
 76. The structure of claim 75, whereinthe container layer includes hemispherical grain polysilicon.
 77. Thestructure of claim 75, wherein the container layer is conductivelydoped.
 78. The structure of claim 75, wherein the container layer is onthe insulating layer.
 79. The structure of claim 75, wherein an exposed,positive-type resist layer extends over the container layer and theunder-exposed, positive-type resist layer.
 80. The structure of claim75, wherein the cone-like structure is convex.
 81. The structure ofclaim 75, wherein the resist layer is adapted to be removed to exposethe container layer.
 82. The structure of claim 81, wherein a dielectriclayer is formed on the exposed portion of the container layer.
 83. Aprocessing stage semiconductor die, comprising a substrate and aplurality of integrated circuit devices on the substrate, wherein atleast one of the plurality of integrated circuit devices includes aprocessing stage container capacitor, the container capacitor including:an insulating layer on the substrate; a container hole in the insulatinglayer having a closed bottom, an open top and sidewalls extendingbetween the closed bottom and open top; a container layer on thesidewalls and closed bottom of the container hole; and an under-exposed,positive-type resist layer in the container hole covering a portion ofthe container layer, wherein a surface of the resist layer open to theopen top is non-planar.
 84. The die of claim 83, wherein the containerlayer includes hemispherical grain polysilicon.
 85. The die of claim 83,wherein the container layer is conductively doped.
 86. The die of claim83, wherein the container layer is on the insulating layer.
 87. The dieof claim 83, wherein an exposed, positive-type resist layer extends overthe container layer and the under-exposed, positive-type resist layer.88. The die of claim 83, wherein the surface of the resist layer isconcave.
 89. The die of claim 83, wherein the surface of the resistlayer is convex.
 90. The die of claim 83, wherein the resist layer isadapted to be removed to expose the container layer.
 91. A processingstage semiconductor die, comprising a substrate and a plurality ofintegrated circuit devices on the substrate, wherein at least one of theplurality of integrated circuit devices includes a processing stagecontainer capacitor, the container capacitor including: an insulatinglayer on the substrate; a container hole in the insulating layer havinga closed bottom, an open top and sidewalls extending between the closedbottom and open top; a container layer on the sidewalls and closedbottom of the container hole; and an under-exposed, positive-type resistlayer in the container hole covering a portion of the container layer,wherein a surface of the resist layer at the open top has a cone-likestructure.
 92. The die of claim 91, wherein the container layer includeshemispherical grain polysilicon.
 93. The die of claim 91, wherein thecontainer layer is conductively doped.
 94. The die of claim 91, whereinthe container layer is on the insulating layer.
 95. The die of claim 91,wherein an exposed, positive-type resist layer extends over thecontainer layer and the under-exposed, positive-type resist layer. 96.The die of claim 91, wherein the cone-like structure is convex.
 97. Thedie of claim 91, wherein the resist layer is adapted to be removed toexpose the container layer.
 98. The die of claim 97, wherein adielectric layer is formed on the exposed portion of the containerlayer.
 99. A processing stage memory cell, comprising: a substrate; aninsulating layer on the substrate; a container hole in the insulatinglayer having a closed bottom, an open top and sidewalls extendingbetween the closed bottom and open top; a container layer on thesidewalls and closed bottom of the container hole; and an under-exposed,positive-type resist layer in the container hole covering a portion ofthe container layer, wherein a surface of the resist layer open to theopen top is non-planar.
 100. The memory cell of claim 99, wherein thecontainer layer includes hemispherical grain polysilicon.
 101. Thememory cell of claim 99, wherein the container layer is conductivelydoped.
 102. The memory cell of claim 99, wherein the container layer ison the insulating layer.
 103. The memory cell of claim 99, wherein anexposed, positive-type resist layer extends over the container layer andthe under-exposed, positive-type resist layer.
 104. The memory cell ofclaim 99, wherein the surface of the resist layer is concave.
 105. Thememory cell of claim 99, wherein the surface of the resist layer isconvex.
 106. The memory cell of claim 99, wherein the resist layer isadapted to be removed to expose the container layer.
 107. A processingstage memory cell, comprising: a substrate; an insulating layer on thesubstrate; a container hole in the insulating layer having a closedbottom, an open top and sidewalls extending between the closed bottomand open top; a container layer on the sidewalls and closed bottom ofthe container hole; and an under-exposed, positive-type resist layer inthe container hole covering a portion of the container layer, wherein asurface of the resist layer at the open top has a cone-like structure.108. The memory cell of claim 107, wherein the container layer includeshemispherical grain polysilicon.
 109. The memory cell of claim 107,wherein the container layer is conductively doped.
 110. The memory cellof claim 107, wherein the container layer is on the insulating layer.111. The memory cell of claim 107, wherein an exposed, positive-typeresist layer extends over the container layer and the under-exposed,positive-type resist layer.
 112. The memory cell of claim 107, whereinthe cone-like structure is convex.
 113. The memory cell of claim 107,wherein the resist layer is adapted to be removed to expose thecontainer layer.
 114. The memory cell of claim 113, wherein a dielectriclayer is formed on the exposed portion of the container layer.
 115. Thecontainer capacitor of claim 26, wherein the underexposed portion of theresist layer includes a surface at the open top of the container holethat is non-planar.
 116. The container capacitor of claim 115, whereinthe surface of underexposed portion of the resist layer has a cone-likestructure.
 117. The container capacitor of claim 27, wherein theunderexposed portion of the resist layer includes a surface at the opentop of the container hole that is non-planar.
 118. The containercapacitor of claim 117, wherein the surface of underexposed portion ofthe resist layer has a cone-like structure.
 119. The container capacitorof claim 28, wherein the underexposed portion of the resist layerincludes a surface at the open top of the container hole that isnon-planar.
 120. The container capacitor of claim 119, wherein thesurface of underexposed portion of the resist layer has a cone-likestructure.
 121. The container capacitor of claim 29, wherein theunderexposed portion of the resist layer includes a surface at the opentop of the container hole that is non-planar.
 122. The containercapacitor of claim 121, wherein the surface of underexposed portion ofthe resist layer has a cone-like structure.
 123. The container capacitorof claim 30, wherein the underexposed portion of the resist layerincludes a surface at the open top of the container hole that isnon-planar.
 124. The container capacitor of claim 123, wherein thesurface of underexposed portion of the resist layer has a cone-likestructure.
 125. The container capacitor of claim 31, wherein theunderexposed portion of the resist layer includes a surface at the opentop of the container hole that is non-planar.
 126. The containercapacitor of claim 125, wherein the surface of underexposed portion ofthe resist layer has a cone-like structure.
 127. A system for processingan integrated circuit structure, comprising: a wafer support on which awafer containing at least one substrate having an insulating layer, acontainer hole in the insulating layer having a closed bottom, an opentop and sidewalls extending between the closed bottom and open top, acontainer layer on the sidewalls and closed bottom of the containerhole, and a positive-type resist layer in the container hole covering aportion of the container layer; a exposure energy source directed to theresist layer at an angled incident relative to the substrate; andwherein at least one of the wafer support and the exposure energy sourceis rotatable such that exposed portion of the resist at the containersidewalls is approximately equal.
 128. The system of claim 127, whereina surface of the resist layer open to the open top is non-planar. 129.The system of claim 127, wherein the exposure energy source includesenergy on the range of about 125 mJ and 200 mJ.
 130. The system of claim127, wherein the exposure energy source includes electromagneticradiation.
 131. The system of claim 127, wherein the exposure energysource includes UV light.
 132. The system of claim 127, wherein theexposure energy source includes light waves.
 133. The system of claim127, wherein a surface of the resist layer open to the open top iscone-like.
 134. A system for processing an integrated circuit structure,comprising: a wafer support on which a wafer containing at least onesubstrate having an insulating layer, a container hole in the insulatinglayer having a closed bottom, an open top and sidewalls extendingbetween the closed bottom and open top, a container layer on thesidewalls and closed bottom of the container hole, and a positive-typeresist layer in the container hole covering a portion of the containerlayer; a exposure energy source directed to the resist layer at anangled incident relative to the substrate; and wherein at least one ofthe wafer support and the exposure energy source is rotatable about anaxis generally perpendicular to a surface of the insulating layer suchthat exposed portion of the resist at the container sidewalls isapproximately equal.
 135. The system of claim 134, wherein a surface ofthe resist layer open to the open top is non-planar.
 136. The system ofclaim 134, wherein the exposure energy source includes energy on therange of about 125 mJ and 200 mJ.
 137. The system of claim 134, whereinthe exposure energy source includes electromagnetic radiation.
 138. Thesystem of claim 134, wherein the exposure energy source includes UVlight.
 139. The system of claim 134, wherein the exposure energy sourceincludes light waves.
 140. The system of claim 134, wherein a surface ofthe resist layer open to the open top is cone-like.
 141. A system forprocessing an integrated circuit structure, comprising: a wafer supporton which a wafer containing at least one substrate having an insulatinglayer, a container hole in the insulating layer having a closed bottom,an open top and sidewalls extending between the closed bottom and opentop, a container layer on the sidewalls and closed bottom of thecontainer hole, and a positive-type resist layer in the container holecovering a portion of the container layer; a exposure energy sourcedirected to the resist layer at an angled incident relative to thesubstrate; and wherein the wafer support is rotatable such that exposedportion of the resist at the container sidewalls is approximately equal.142. The system of claim 141, wherein a surface of the resist layer opento the open top is non-planar.
 143. The system of claim 141, wherein theexposure energy source includes energy on the range of about 125 mJ and200 mJ.
 144. The system of claim 141, wherein the exposure energy sourceincludes electromagnetic radiation.
 145. The system of claim 141,wherein the exposure energy source includes UV light.
 146. The system ofclaim 141, wherein the exposure energy source includes light waves. 147.The system of claim 141, wherein a surface of the resist layer open tothe open top is cone-like.
 148. A system for processing an integratedcircuit structure, comprising: a wafer support on which a wafercontaining at least one substrate having an insulating layer, acontainer hole in the insulating layer having a closed bottom, an opentop and sidewalls extending between the closed bottom and open top, acontainer layer on the sidewalls and closed bottom of the containerhole, and a positive-type resist layer in the container hole covering aportion of the container layer; a exposure energy source directed to theresist layer at an angled incident relative to the substrate; andwherein the wafer support is rotatable about an axis generallyperpendicular to a surface of the insulating layer such that exposedportion of the resist at the container sidewalls is approximately equal.149. The system of claim 148, wherein a surface of the resist layer opento the open top is non-planar.
 150. The system of claim 148, wherein theexposure energy source includes energy on the range of about 125 mJ and200 mJ.
 151. The system of claim 148, wherein the exposure energy sourceincludes electromagnetic radiation.
 152. The system of claim 148,wherein the exposure energy source includes UV light.
 153. The system ofclaim 148, wherein the exposure energy source includes light waves. 154.The system of claim 148, wherein a surface of the resist layer open tothe open top is cone-like.
 155. A system for processing an integratedcircuit structure, comprising: a wafer support on which a wafercontaining at least one substrate having an insulating layer, acontainer hole in the insulating layer having a closed bottom, an opentop and sidewalls extending between the closed bottom and open top, acontainer layer on the sidewalls and closed bottom of the containerhole, and a positive-type resist layer in the container hole covering aportion of the container layer; a exposure energy source directed to theresist layer at an angled incident relative to the substrate; andwherein the exposure energy source is rotatable such that exposedportion of the resist at the container sidewalls is approximately equal.156. The system of claim 155, wherein a surface of the resist layer opento the open top is non-planar.
 157. The system of claim 155, wherein theexposure energy source includes energy on the range of about 125 mJ and200 mJ.
 158. The system of claim 155, wherein the exposure energy sourceincludes electromagnetic radiation.
 159. The system of claim 155,wherein the exposure energy source includes UV light.
 160. The system ofclaim 155, wherein the exposure energy source includes light waves. 161.The system of claim 155, wherein a surface of the resist layer open tothe open top is cone-like.
 162. A system for processing an integratedcircuit structure, comprising: a wafer support on which a wafercontaining at least one substrate having an insulating layer, acontainer hole in the insulating layer having a closed bottom, an opentop and sidewalls extending between the closed bottom and open top, acontainer layer on the sidewalls and closed bottom of the containerhole, and a positive-type resist layer in the container hole covering aportion of the container layer; a exposure energy source directed to theresist layer at an angled incident relative to the substrate; andwherein the exposure energy source is rotatable about an axis generallyperpendicular to a surface of the insulating layer such that exposedportion of the resist at the container sidewalls is approximately equal.163. The system of claim 162, wherein a surface of the resist layer opento the open top is non-planar.
 164. The system of claim 162, wherein theexposure energy source includes energy on the range of about 125 mJ and200 mJ.
 165. The system of claim 162, wherein the exposure energy sourceincludes electromagnetic radiation.
 166. The system of claim 162,wherein the exposure energy source includes UV light.
 167. The system ofclaim 162, wherein the exposure energy source includes light waves. 168.The system of claim 162, wherein a surface of the resist layer open tothe open top is cone-like.